1. Field of the Invention
The present invention relates to a process for manufacturing an array of cells including selection bipolar junction transistors. In particular, the invention refers to a memory array of a phase change memory (PCM) device, without being limited thereto.
2. Description of the Related Art
As is known, phase change memory cells utilize a class of materials that have the unique property of being reversibly switchable from one phase to another with measurable distinct resistivity. Specific materials that may be suitably used in phase change memory cells are alloys of elements of the VI group of the periodic table as Te or Se, also called chalcogenides or chalcogenic materials. Thus a thin film of chalcogenic material may be employed as a programmable resistor, switching between a high and a low resistance condition.
The use of chalcogenic storage elements has been already proposed to form a memory cell. To avoid disturbances caused by adjacent memory cells, the chalcogenic element is generally coupled with a selection element, generally a MOS transistor or a diode.
A possible organization of a PCM array is shown in FIG. 1. The memory array 1 of FIG. 1 comprises a plurality of memory cells 2, each including a storage element 3 of the phase change type and a selection element 4 formed here as a diode.
The memory cells 2 are arranged on rows and columns. In each memory cell 2, the storage element 3 has a first terminal connected to an own bit line BLn−1, BLn, BLn+1, . . . , and a second terminal connected to an anode of the diode 4; the diode 4 has a cathode connected to an own word line WLn−1, WLn, WLn+1, . . .
In order to address the storage element 3 belonging to a specific cell 2, for example the one connected to bit line BLn and to world line WLn, the bit line connected to the addressed cell (selected bit line BLn) is biased at a high voltage VOP and all the other (unselected) bit lines BLn−1, BLn+1, . . . are grounded. Furthermore, the word line connected to the addressed cell (selected word line WLn) is grounded and all the other (unselected) word lines WLn−1, WLn+1, . . . are biased at VCC, so that only the diode 4 connected to the selected word line and bit line is on.
CMOS compatible processes for manufacturing PCM have been already proposed, wherein the diodes are integrated in a P-type substrate wherein N-type regions are formed. The N-type regions, defining the cathode of the diodes, are contacted by a metal line and form wordlines of the array. The N-type regions accommodate P-type regions that define the anodes of the diodes and are connected to long stripes of chalcogenic material at small portions thereof defining the storage elements. The stripes of chalcogenic material extend perpendicular to the wordlines and define bitlines of the array.
Because of this structure, the diodes are associated with parasitic bipolar transistors having emitters formed by the diode anodes and connected to the bitlines (here, bitline BLn); bases formed by the diode cathodes and connected to the wordlines (here, wordline WLn); and collectors formed by the substrate. The equivalent electric diagram of a real cell is shown of FIG. 2.
In practice, selection of a cell 2 is done by driving the bipolar transistor 4 in the active region and biasing the base-emitter junction in direct mode. Therefore, the actual current IB supplied by the base terminal is not equal to the current IE flowing through the emitter terminal, but is defined by the following relationship:IB=IE/(1+βF)wherein βF is the current gain of the bipolar transistor.
The presence of these parasitic transistors causes some problems, mainly due to the high currents flowing in particular during a modify (set, reset) operation. Indeed, usually a write operation is performed on a number of cells on a single wordline (eight or sixteen cells, or even more) so that the total current flowing through the selected wordline and in the decoder drive pull-down transistor is the sum of the currents of the cells. This poses an upper limit to the number of cells that can be modified in a single operation, because the voltage drop across the selected wordline and the pull-down transistor becomes unacceptable.
Indeed, during a modify operation, a current in the range of 200 μA flows through the emitter terminal of each bipolar transistor 4. Since, as said, eight or sixteen cells connected to a same wordline are modified at the same time, the total current entering the emitters of the selected transistors is 1.6–3.2 mA.
Since in known memory arrays the bipolar transistor is not exploited, but instead it is considered a parasitic element, its design is not optimized, so that its current gain βF is much less than 1, the current flowing in the selected wordline is about the same as the total emitter current (1.6–3.2 mA, as above discussed); this current flows along the entire wordline and in the pull-down transistor of the row decoder, causing an unacceptable voltage drop.